IP PortfolioPhysical IPi/o pads
of_io_cml
CML / LVPECL clock I/O
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
Current-mode logic input and output buffers for high-speed reference clocks, AC or DC coupled, with internal termination.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| pad | inout | analog | 2 | |
| clk_out | out | clock | 1 |
Standards
No external standard applies.
More in i/o pads
| ID | Block | Maturity |
|---|---|---|
| of_io_gpio | General-purpose I/O cell | planned |
| of_io_failsafe | Fail-safe and 5 V tolerant I/O | planned |
| of_io_od | Open-drain I2C / I3C I/O | planned |
| of_io_lvds | LVDS I/O cells | planned |
| of_io_sstl | SSTL / POD memory I/O cells | planned |
| of_io_analog | Analog pad | planned |
| of_io_rf | RF pad | planned |
| of_io_xtal | Crystal oscillator I/O cell | planned |
| of_io_power | Power and ground pads | planned |
| of_io_corner_filler | I/O corner and filler cells | planned |