IP PortfolioPhysical IPi/o pads
of_io_sstl
SSTL / POD memory I/O cells
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
Memory interface pads supporting SSTL and POD signaling with calibrated output impedance, programmable ODT and VREF input.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| pad | inout | analog | 1 | |
| a | in | parallel | 1 | |
| oe | in | parallel | 1 | |
| y | out | parallel | 1 |
Standards
- JEDEC JESD79-4
- JEDEC JESD79-5
- JEDEC JESD8-24
More in i/o pads
| ID | Block | Maturity |
|---|---|---|
| of_io_gpio | General-purpose I/O cell | planned |
| of_io_failsafe | Fail-safe and 5 V tolerant I/O | planned |
| of_io_od | Open-drain I2C / I3C I/O | planned |
| of_io_lvds | LVDS I/O cells | planned |
| of_io_cml | CML / LVPECL clock I/O | planned |
| of_io_analog | Analog pad | planned |
| of_io_rf | RF pad | planned |
| of_io_xtal | Crystal oscillator I/O cell | planned |
| of_io_power | Power and ground pads | planned |
| of_io_corner_filler | I/O corner and filler cells | planned |