IP PortfolioPhysical IPmemory compilers
of_mc_edram
Gain-cell embedded DRAM compiler
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
Logic-compatible 2T/3T gain-cell eDRAM macros with refresh controller interface, for dense on-chip buffers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| port_a | in | valid-qualified bus | 64 | |
| rdata | out | parallel | 64 |
Standards
- Liberty
More in memory compilers
| ID | Block | Maturity |
|---|---|---|
| of_mc_sram_sp | Single-port SRAM compiler | planned |
| of_mc_sram_dp | True dual-port SRAM compiler | planned |
| of_mc_sram_2p | Two-port (1R1W) SRAM compiler | planned |
| of_mc_rf | Register-file compiler | planned |
| of_mc_sram_lv | Low-voltage 8T SRAM compiler | planned |
| of_mc_rom | ROM compiler | planned |
| of_mc_cam | CAM and TCAM compiler | planned |
| of_mc_cim | Compute-in-memory SRAM macro | planned |
| of_mc_sram_rt | Radiation-tolerant SRAM compiler | planned |