IP PortfolioPhysical IPmemory compilers
of_mc_sram_2p
Two-port (1R1W) SRAM compiler
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 1
Compiler for one-read one-write SRAM macros with separate read and write clocks, for FIFOs and buffers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| wr | in | valid-qualified bus | 64 | |
| rd | out | valid-qualified bus | 64 | |
| rd_clk | in | clock | 1 |
Standards
- Liberty
- LEF/DEF 5.8
Basis projects
Permissive open projects the implementation may build on.
- OpenRAM (BSD-3-Clause)
More in memory compilers
| ID | Block | Maturity |
|---|---|---|
| of_mc_sram_sp | Single-port SRAM compiler | planned |
| of_mc_sram_dp | True dual-port SRAM compiler | planned |
| of_mc_rf | Register-file compiler | planned |
| of_mc_sram_lv | Low-voltage 8T SRAM compiler | planned |
| of_mc_rom | ROM compiler | planned |
| of_mc_cam | CAM and TCAM compiler | planned |
| of_mc_edram | Gain-cell embedded DRAM compiler | planned |
| of_mc_cim | Compute-in-memory SRAM macro | planned |
| of_mc_sram_rt | Radiation-tolerant SRAM compiler | planned |