IP PortfolioPhysical IPphysical-only cells

of_sc_tap

Well tap cells

Maturity plannedTargets ASIC (CMOS) onlyDifficulty EasyPriority 1

N-well and substrate tap cells placed at fixed pitch to meet latch-up rules, with variants for row ends and power-gated wells.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

No external interfaces are defined for this entry yet.

Standards

  • LEF/DEF 5.8

Basis projects

Permissive open projects the implementation may build on.

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