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of_cpri

CPRI link controller

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3

CPRI radio equipment controller and radio equipment link with line rates options 1 to 10, hyperframe framing, IQ mapping, control and management channels and delay measurement.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAXI4-Lite control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
phy_txoutparallel64 
phy_rxinparallel64 
iq_txinAXI4-Stream64 
iq_rxoutAXI4-Stream64 

Standards

  • CPRI Specification V7.0

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