IP PortfolioInterface controllersfronthaul
of_ecpri
eCPRI framer
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
eCPRI message framing over Ethernet or UDP for IQ data, real-time control and one-way delay measurement messages.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| mac_tx | out | AXI4-Stream | 64 | |
| mac_rx | in | AXI4-Stream | 64 | |
| iq_tx | in | AXI4-Stream | 64 | |
| iq_rx | out | AXI4-Stream | 64 |
Standards
- eCPRI Specification V2.0
More in fronthaul
| ID | Block | Maturity |
|---|---|---|
| of_cpri | CPRI link controller | planned |
| of_oran_fh | O-RAN fronthaul C/U-plane engine | planned |