IP PortfolioInterface controllersmanagement
of_espi
eSPI controller and target
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
Enhanced SPI controller or target with peripheral, virtual wire, out-of-band and flash access channels for PC and server platform chipsets and BMCs.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| espi_clk | inout | clock | 1 | |
| espi_cs_n | inout | serial | 1 | |
| espi_io | inout | parallel | 4 | |
| alert_n | inout | serial | 1 |
Standards
- Intel eSPI Base Specification 1.0