IP PortfolioInterface controllersmanagement
of_lpc
LPC bus host and peripheral
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
Low Pin Count bus host or peripheral with I/O, memory, firmware hub and serial IRQ cycles for legacy platform devices.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| lad | inout | parallel | 4 | |
| lframe_n | inout | serial | 1 | |
| serirq | inout | serial | 1 |
Standards
- Intel LPC Interface Specification 1.1