IP PortfolioInterface controllersaudio
of_i2s_tdm
I2S / TDM audio port
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Audio serial port supporting I2S, left-justified and TDM formats with up to 16 slots, 8 to 32 bit samples, master or slave clocking and AXI-Stream sample paths.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| bclk | inout | clock | 1 | |
| lrclk | inout | serial | 1 | |
| sdo | out | serial | 4 | |
| sdi | in | serial | 4 | |
| play | in | AXI4-Stream | 32 | |
| rec | out | AXI4-Stream | 32 |
Standards
- Philips I2S bus specification (1996)
Basis projects
Permissive open projects the implementation may build on.
- LiteX (BSD-2-Clause)
More in audio
| ID | Block | Maturity |
|---|---|---|
| of_pdm_mic | PDM microphone interface | planned |
| of_soundwire | MIPI SoundWire manager | planned |
| of_spdif | S/PDIF transmitter and receiver | planned |