IP PortfolioInterface controllersconverter_link
of_jesd204b
JESD204B link layer
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
JESD204B transmit and receive link layers with 8b/10b, code group sync, ILAS, scrambling and subclass 1 SYSREF deterministic latency.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phy_tx | out | parallel | 128 | |
| phy_rx | in | parallel | 128 | |
| samples_tx | in | AXI4-Stream | 128 | |
| samples_rx | out | AXI4-Stream | 128 | |
| sysref | in | serial | 1 |
Standards
- JEDEC JESD204B
Basis projects
Permissive open projects the implementation may build on.
- LiteJESD204B (BSD-2-Clause)
More in converter_link
| ID | Block | Maturity |
|---|---|---|
| of_jesd204c | JESD204C link layer | planned |
| of_jesd204d | JESD204D link layer | planned |