IP PortfolioInterface controllersdebug
of_swd_dp
Serial Wire Debug port
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Arm SW-DP with line reset, packet parsing, parity, ACK handling and an access-port bus for memory and debug register access.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| swclk | in | clock | 1 | |
| swdio | inout | serial | 1 | |
| ap_req | out | valid-qualified bus | 64 | |
| ap_rsp | in | valid-qualified bus | 33 |
Standards
- Arm ADIv5.2
- Arm ADIv6.0
More in debug
| ID | Block | Maturity |
|---|---|---|
| of_cjtag | Compact JTAG (IEEE 1149.7) adapter | planned |