IP PortfolioInterface controllerslin
of_lin
LIN commander/responder
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
LIN controller with commander schedule table and responder modes, break and sync detection, auto-baud, classic and enhanced checksum.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| lin_tx | out | serial | 1 | |
| lin_rx | in | serial | 1 |
Standards
- ISO 17987-3:2016
- LIN 2.2A