IP PortfolioInterface controllersethernet_offload
of_macsec_framer
MACsec SecTAG framer
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
MACsec frame processing without the cipher: SecTAG insertion and parsing, SCI and packet-number tracking, replay window and ICV placement, with an AXI-Stream port to an external AES-GCM core.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| tx_in | in | AXI4-Stream | 128 | |
| tx_out | out | AXI4-Stream | 128 | |
| rx_in | in | AXI4-Stream | 128 | |
| rx_out | out | AXI4-Stream | 128 | |
| crypto_req | out | AXI4-Stream | 128 | |
| crypto_rsp | in | AXI4-Stream | 128 |
Standards
- IEEE 802.1AE-2018
Notes
AES-GCM is supplied by the security catalog; this block alone provides no confidentiality.
More in ethernet_offload
| ID | Block | Maturity |
|---|---|---|
| of_eth_ptp_tsu | IEEE 1588 PTP timestamping unit | simulated |
| of_udp_ip_offload | UDP/IPv4 offload engine | planned |
| of_tcp_offload | TCP offload engine | planned |
| of_roce_v2 | RoCE v2 RDMA engine | planned |
| of_uet_transport | Ultra Ethernet transport engine | planned |
| of_ncsi | NC-SI sideband controller | planned |