IP PortfolioInterface controllersethernet_offload
of_uet_transport
Ultra Ethernet transport engine
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Hardware packet delivery and semantic sublayers of the Ultra Ethernet transport with packet spraying, selective retransmission and congestion control for AI and HPC fabrics.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| mac_tx | out | AXI4-Stream | 512 | |
| mac_rx | in | AXI4-Stream | 512 | |
| dma_rd | out | AXI4-Stream | 512 | |
| dma_wr | in | AXI4-Stream | 512 |
Standards
- Ultra Ethernet Specification 1.0
More in ethernet_offload
| ID | Block | Maturity |
|---|---|---|
| of_eth_ptp_tsu | IEEE 1588 PTP timestamping unit | simulated |
| of_udp_ip_offload | UDP/IPv4 offload engine | planned |
| of_tcp_offload | TCP offload engine | planned |
| of_roce_v2 | RoCE v2 RDMA engine | planned |
| of_macsec_framer | MACsec SecTAG framer | planned |
| of_ncsi | NC-SI sideband controller | planned |