of_nand_ctrl

NAND flash controller (ONFI/Toggle)

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2

Raw NAND controller with ONFI NV-DDR3 and Toggle DDR modes, multi-plane and cache commands, command sequencer, DMA and pluggable BCH or LDPC ECC interface.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
dq	inout	parallel	8
dqs	inout	differential pair	1
ctl	out	parallel	8
rb_n	in	parallel	4
ecc_out	out	AXI4-Stream	64
ecc_in	in	AXI4-Stream	64

Standards

ONFI 5.0
JEDEC JESD230