IP PortfolioInterface controllerssd_mmc
of_sd_host
SD/SDIO host controller
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
SD and SDIO host with 1/4-bit bus, default to UHS-I SDR104 timing, ADMA2 descriptor DMA and tuning support.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| clk_sd | out | clock | 1 | |
| cmd | inout | serial | 1 | |
| dat | inout | parallel | 4 |
Standards
- SD Physical Layer Specification 3.01
- SD Host Controller Specification 3.00
- SDIO Specification 3.00
Basis projects
Permissive open projects the implementation may build on.
- LiteSDCard (BSD-2-Clause)
More in sd_mmc
| ID | Block | Maturity |
|---|---|---|
| of_emmc_host | eMMC 5.1 host controller | planned |
| of_sdio_device | SDIO device controller | planned |