IP PortfolioInterface controllersnvme
of_nvme_host
NVMe host initiator
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Hardware NVMe initiator that builds submission and completion queues, rings doorbells and moves data through a PCIe root port without a host CPU.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| data_wr | in | AXI4-Stream | 256 | |
| data_rd | out | AXI4-Stream | 256 | |
| pcie_tlp | out | AXI4-Stream | 256 |
Standards
- NVM Express Base Specification 2.0
More in nvme
| ID | Block | Maturity |
|---|---|---|
| of_nvme_target | NVMe device controller | planned |