of_sata_host

SATA host controller (AHCI)

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2

SATA 6 Gb/s host with link and transport layers, NCQ, port multiplier support and AHCI register interface over a PIPE-style PHY interface.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
phy_tx	out	parallel	32
phy_rx	in	parallel	32

Standards

Serial ATA Revision 3.5
Serial ATA AHCI 1.3.1

Basis projects

Permissive open projects the implementation may build on.

LiteSATA (BSD-2-Clause)