IP PortfolioInterface controllerslow_speed
of_onewire
1-Wire master
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
1-Wire bus master with reset/presence detection, standard and overdrive timing, ROM search acceleration and CRC-8 checking.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| owire | inout | serial | 1 |
Standards
No external standard applies.