IP PortfolioInterface controllerspcie
of_pcie_dma
PCIe multi-channel DMA engine
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Descriptor-based scatter-gather DMA for PCIe endpoints with host-to-card and card-to-host channels, MSI-X interrupt generation and AXI-Stream or AXI memory-mapped user ports.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| tlp_tx | out | AXI4-Stream | 512 | |
| tlp_rx | in | AXI4-Stream | 512 | |
| h2c | out | AXI4-Stream | 512 | |
| c2h | in | AXI4-Stream | 512 |
Standards
- PCI Express Base 5.0
Basis projects
Permissive open projects the implementation may build on.
- verilog-pcie (MIT)
More in pcie
| ID | Block | Maturity |
|---|---|---|
| of_pcie_g3_ctrl | PCIe Gen3 controller (EP/RP) | planned |
| of_pcie_g4_ctrl | PCIe Gen4 controller (EP/RP) | planned |
| of_pcie_g5_ctrl | PCIe Gen5 controller (EP/RP) | planned |
| of_pcie_g6_ctrl | PCIe Gen6 controller (EP/RP) | planned |
| of_pcie_g7_ctrl | PCIe Gen7 controller (EP/RP) | planned |
| of_pcie_switch | PCIe switch | planned |