IP PortfolioInterface controllerspcie
of_pcie_g5_ctrl
PCIe Gen5 controller (EP/RP)
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
PCI Express controller up to Gen5 operable as endpoint or root port, with transaction, data link and PHY logical layers, SR-IOV option and a PIPE interface. Adds 32 GT/s, alternate protocol negotiation used by CXL and precoding.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pipe_tx | out | parallel | 512 | |
| pipe_rx | in | parallel | 512 | |
| tlp_tx | in | AXI4-Stream | 512 | |
| tlp_rx | out | AXI4-Stream | 512 |
Standards
- PCI Express Base 5.0
- Intel PIPE 5.1
More in pcie
| ID | Block | Maturity |
|---|---|---|
| of_pcie_g3_ctrl | PCIe Gen3 controller (EP/RP) | planned |
| of_pcie_g4_ctrl | PCIe Gen4 controller (EP/RP) | planned |
| of_pcie_g6_ctrl | PCIe Gen6 controller (EP/RP) | planned |
| of_pcie_g7_ctrl | PCIe Gen7 controller (EP/RP) | planned |
| of_pcie_switch | PCIe switch | planned |
| of_pcie_dma | PCIe multi-channel DMA engine | planned |