IP PortfolioInterface controllerssensor_bus
of_psi5
PSI5 receiver
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
PSI5 current-modulated sensor interface receiver controller with synchronous and asynchronous modes, Manchester decoding, parity/CRC and sync pulse generation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| psi5_rx | in | parallel | 4 | |
| psi5_sync | out | parallel | 4 |
Standards
- PSI5 Technical Specification v2.3
More in sensor_bus
| ID | Block | Maturity |
|---|---|---|
| of_sent | SENT receiver | planned |