IP PortfolioInterface controllerssensor_bus
of_sent
SENT receiver
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
SAE J2716 SENT receiver for up to 4 channels with tick calibration, nibble decoding, CRC checking and slow serial message assembly.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| sent_in | in | parallel | 4 |
Standards
- SAE J2716
More in sensor_bus
| ID | Block | Maturity |
|---|---|---|
| of_psi5 | PSI5 receiver | planned |