IP PortfolioInterface controllerssd_mmc
of_sdio_device
SDIO device controller
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
SDIO card-side controller for wireless and peripheral chips with CIS/CCCR registers, function 1 to 7 windows and block transfers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| clk_sd | in | clock | 1 | |
| cmd | inout | serial | 1 | |
| dat | inout | parallel | 4 |
Standards
- SDIO Specification 3.00
More in sd_mmc
| ID | Block | Maturity |
|---|---|---|
| of_sd_host | SD/SDIO host controller | simulated |
| of_emmc_host | eMMC 5.1 host controller | planned |