IP PortfolioInterface PHYsdie_to_die_phy
of_aib_phy
AIB PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
Advanced Interface Bus I/O columns with DDR data, forwarded clocks, DLL-based deskew and redundancy for EMIB and interposer packaging.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| io | inout | parallel | 80 | |
| par_tx | in | parallel | 320 | |
| par_rx | out | parallel | 320 |
Standards
- CHIPS Alliance AIB 2.0
More in die_to_die_phy
| ID | Block | Maturity |
|---|---|---|
| of_ucie_phy_std | UCIe standard-package PHY | planned |
| of_ucie_phy_adv | UCIe advanced-package PHY | planned |
| of_bow_phy | BoW die-to-die PHY | planned |
| of_openhbi_phy | OpenHBI PHY | planned |
| of_d2d_xsr_serdes | 112G XSR die-to-die SerDes | planned |