IP PortfolioInterface PHYsdie_to_die_phy
of_ucie_phy_std
UCIe standard-package PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 1
UCIe PHY for organic substrate packages with x16 modules, forwarded clock, lane repair, sideband channel and RDI interface.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | parallel | 16 | |
| rx | in | parallel | 16 | |
| fwd_clk | inout | differential pair | 2 | |
| sideband | inout | parallel | 4 | |
| rdi_tx | in | parallel | 512 | |
| rdi_rx | out | parallel | 512 |
Standards
- UCIe 2.0
More in die_to_die_phy
| ID | Block | Maturity |
|---|---|---|
| of_ucie_phy_adv | UCIe advanced-package PHY | planned |
| of_bow_phy | BoW die-to-die PHY | planned |
| of_aib_phy | AIB PHY | planned |
| of_openhbi_phy | OpenHBI PHY | planned |
| of_d2d_xsr_serdes | 112G XSR die-to-die SerDes | planned |