IP PortfolioInterface PHYsoptical_phy
of_pam4_optical_dsp
PAM4 optical module DSP PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
Optical module DSP with host-side 112G SerDes, line-side PAM4 DSP with FFE/MLSE, FEC and gearbox for 400G/800G pluggables.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| host_tx | out | differential pair | 8 | |
| host_rx | in | differential pair | 8 | |
| line_tx | out | differential pair | 8 | |
| line_rx | in | differential pair | 8 | |
| refclk | in | differential pair | 1 |
Standards
- IEEE 802.3ck-2022
- IEEE 802.3df-2024
- OIF CEI-112G-VSR
More in optical_phy
| ID | Block | Maturity |
|---|---|---|
| of_vcsel_driver | VCSEL driver array | planned |
| of_pd_tia | Photodiode TIA array | planned |
| of_sipho_mod_driver | Silicon photonics modulator driver | planned |
| of_ring_tuning_ctrl | Micro-ring resonance tuning controller | planned |
| of_cpo_engine_if | Co-packaged optics electrical interface | planned |
| of_lpo_linear_frontend | Linear pluggable optics driver and TIA | planned |