IP PortfolioInterface PHYspcie_phy
of_pcie_g5_phy
PCIe Gen5 PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 1
PCI Express PHY up to 32 GT/s with PIPE interface, x1 to x16 lane configurations, receiver detection, electrical idle and L1 substates. Supports CXL alternate protocol and precoding.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 4 | |
| rx | in | differential pair | 4 | |
| refclk | in | differential pair | 1 | |
| pma_tx | in | parallel | 256 | |
| pma_rx | out | parallel | 256 |
Standards
- PCI Express Base 5.0
- Intel PIPE 5.1
More in pcie_phy
| ID | Block | Maturity |
|---|---|---|
| of_pcie_g3_phy | PCIe Gen3 PHY | planned |
| of_pcie_g4_phy | PCIe Gen4 PHY | planned |
| of_pcie_g6_phy | PCIe Gen6 PHY | planned |
| of_pcie_g7_phy | PCIe Gen7 PHY | planned |
| of_pcie_retimer | PCIe/CXL retimer | planned |