IP PortfolioInterface PHYspcie_phy
of_pcie_retimer
PCIe/CXL retimer
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
Protocol-aware PCIe and CXL retimer with per-lane CDR, full equalisation, LTSSM participation and SRIS/SSC handling for long board and cable channels.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| a_tx | out | differential pair | 16 | |
| a_rx | in | differential pair | 16 | |
| b_tx | out | differential pair | 16 | |
| b_rx | in | differential pair | 16 | |
| refclk | in | differential pair | 1 |
Standards
- PCI Express Base 6.0
- CXL 3.1
More in pcie_phy
| ID | Block | Maturity |
|---|---|---|
| of_pcie_g3_phy | PCIe Gen3 PHY | planned |
| of_pcie_g4_phy | PCIe Gen4 PHY | planned |
| of_pcie_g5_phy | PCIe Gen5 PHY | planned |
| of_pcie_g6_phy | PCIe Gen6 PHY | planned |
| of_pcie_g7_phy | PCIe Gen7 PHY | planned |