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of_mm_isp_pipeline

Integrated camera ISP pipeline

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1

Configurable composition of the raw-domain, RGB and YUV ISP stages with frame-level control and statistics DMA.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

PortDirectionKindWidthNotes
ctrlin/outAXI4-Lite control bus32Control and status registers, including ID, VERSION and STATUS
irqoutinterrupt1Interrupt request
raw_ininAXI4-Stream16 
pix_outoutAXI4-Stream30 

Standards

  • MIPI CSI-2

Notes

Composite of the of_mm_isp_* stage entries.

More in isp

IDBlockMaturity
of_mm_isp_blcBlack level correctionsimulated
of_mm_isp_dpcDefect pixel correctionsimulated
of_mm_isp_lscLens shading correctionsimulated
of_mm_isp_demosaicBayer demosaicsimulated
of_mm_isp_3a_statsAuto exposure, white balance and focus statisticssimulated
of_mm_isp_awb_gainWhite balance gain and colour correction matrixsimulated
of_mm_isp_gammaGamma and tone curve LUTsimulated
of_mm_isp_hdr_mergeMulti-exposure HDR mergeplanned
of_mm_isp_tonemapLocal tone mappingplanned
of_mm_isp_nr2dSpatial noise reductionsimulated