IP PortfolioProcessorsbranch_pred
of_cpu_bp_gshare
Branch predictor for in-order cores
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Configurable bimodal or gshare direction predictor with branch target buffer and return address stack, sized for in-order pipelines.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| fetch_pc | in | valid-qualified bus | 64 | |
| pred | out | valid-qualified bus | 66 | |
| update | in | valid-qualified bus | 130 |
Standards
No external standard applies.
More in branch_pred
| ID | Block | Maturity |
|---|---|---|
| of_cpu_bp_tage | TAGE-class branch predictor | planned |