IP PortfolioProcessors

Processors and microcontrollers

RISC-V cores from tiny to application class, DSP cores, vector and SIMD units, real-time and safety cores, microcontroller subsystems, debug modules.

Blocks 94Implemented 19Families 24FPGA + ASIC 94

riscv_mcu

6 blocks · 3 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_rv32e_tiny	RV32E minimal core	simulated	FPGA + ASIC	Easy
of_cpu_rv32_bitserial	Bit-serial RV32I core	planned	FPGA + ASIC	Easy
of_cpu_rv32imc_mcu	RV32IMC microcontroller core	simulated	FPGA + ASIC	Medium
of_cpu_rv32imac_zc_mcu	RV32IMAC core with Zb and Zc	planned	FPGA + ASIC	Medium
of_cpu_rv32imfc_perf	RV32IMFC performance MCU core	simulated	FPGA + ASIC	Medium
of_cpu_rv32_dual_issue	Dual-issue in-order RV32 core	planned	FPGA + ASIC	Hard

riscv_rt

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_rv32_rt_clic	Real-time RV32 core with CLIC	planned	FPGA + ASIC	Hard
of_cpu_rv64_realtime	RV64 real-time core with MPU	planned	FPGA + ASIC	Hard

riscv_safety

4 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_rv32_lockstep	Dual-core lockstep RV32 safety core	planned	FPGA + ASIC	Hard
of_cpu_rv64_lockstep	Lockstep RV64 application core	planned	FPGA + ASIC	Very hard
of_cpu_lockstep_checker	Lockstep comparator and delay unit	simulated	FPGA + ASIC	Medium
of_cpu_safety_island	Safety island subsystem	planned	FPGA + ASIC	Hard

riscv_app

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_rv64_inorder	RV64GC single-issue application core	planned	FPGA + ASIC	Hard
of_cpu_rv64_dual_issue	RV64GC dual-issue in-order core	planned	FPGA + ASIC	Very hard

riscv_ooo

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_rv64_ooo	RV64GC out-of-order core	planned	FPGA + ASIC	Very hard
of_cpu_rva23_server	RVA23 server-class out-of-order core	planned	FPGA + ASIC	Very hard

riscv_vector

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_rvv_unit	RISC-V vector unit	planned	FPGA + ASIC	Very hard
of_cpu_zve32_embedded_vector	Embedded vector extension unit	planned	FPGA + ASIC	Hard
of_cpu_rv64gcv_app	RV64GCV in-order core with integrated vector	planned	FPGA + ASIC	Very hard

riscv_cluster

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_cluster_coherent	Coherent RV64 multicore cluster	planned	FPGA + ASIC	Very hard
of_cpu_cluster_tcdm	Shared-memory RV32 compute cluster	planned	FPGA + ASIC	Hard
of_cpu_manycore_tile	Many-core mesh tile	planned	FPGA + ASIC	Very hard
of_cpu_acp	Accelerator coherency port	planned	FPGA + ASIC	Hard

riscv_multithread

2 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_mt_barrel	Fine-grained multithreaded core	planned	FPGA + ASIC	Hard
of_cpu_smt2_ooo_ext	Two-way SMT extension	planned	FPGA + ASIC	Very hard

riscv_secure

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_rv32_secure	Security-hardened RV32 core	planned	FPGA + ASIC	Hard
of_cpu_cheriot_mcu	CHERIoT capability microcontroller core	planned	FPGA + ASIC	Hard
of_cpu_rv64_cheri	CHERI RV64 application core	planned	FPGA + ASIC	Very hard
of_cpu_world_isolation	Hardware world isolation checker	planned	FPGA + ASIC	Medium

mmu

2 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_pmp_unit	PMP and ePMP checker	simulated	FPGA + ASIC	Easy
of_cpu_mmu	MMU with TLBs and page table walker	planned	FPGA + ASIC	Hard

dsp

7 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_dsp_vliw	VLIW DSP core	planned	FPGA + ASIC	Very hard
of_dsp_audio	Audio DSP core	planned	FPGA + ASIC	Hard
of_dsp_baseband	Baseband DSP core	planned	FPGA + ASIC	Very hard
of_dsp_vision	Vision DSP core	planned	FPGA + ASIC	Very hard
of_dsp_radar	Radar signal processing DSP	planned	FPGA + ASIC	Hard
of_dsp_motor_control	Motor control coprocessor	planned	FPGA + ASIC	Medium
of_dsp_sensor_hub	Sensor fusion DSP	planned	FPGA + ASIC	Medium

isa_ext

9 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_ext_bitmanip	Bit-manipulation extension unit	simulated	FPGA + ASIC	Easy
of_cpu_ext_scalar_crypto	Scalar cryptography extension unit	simulated	FPGA + ASIC	Medium
of_cpu_ext_vector_crypto	Vector cryptography extension unit	planned	FPGA + ASIC	Hard
of_cpu_ext_packed_simd	Packed SIMD extension unit	planned	FPGA + ASIC	Medium
of_cpu_ext_matrix	Matrix extension unit	planned	FPGA + ASIC	Very hard
of_cpu_ext_dot_product	Packed dot-product extension	planned	FPGA + ASIC	Medium
of_cpu_ext_dsp_hwloop	Hardware loop and addressing extension	planned	FPGA + ASIC	Medium
of_cpu_xif_adapter	CORE-V eXtension Interface adapter	planned	FPGA + ASIC	Medium
of_cpu_ext_cfi	Control-flow integrity extension unit	planned	FPGA + ASIC	Medium

fpu

2 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_fpu_multiformat	Multi-format pipelined FPU	simulated	FPGA + ASIC	Hard
of_cpu_fpu_compact	Area-optimised iterative FPU	planned	FPGA + ASIC	Medium

hypervisor

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_hypervisor_ext	Hypervisor extension unit	planned	FPGA + ASIC	Very hard

branch_pred

2 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_bp_gshare	Branch predictor for in-order cores	simulated	FPGA + ASIC	Medium
of_cpu_bp_tage	TAGE-class branch predictor	planned	FPGA + ASIC	Hard

cache

7 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_l1i_cache	L1 instruction cache	simulated	FPGA + ASIC	Medium
of_cpu_l1d_cache	L1 data cache	planned	FPGA + ASIC	Hard
of_cpu_l2_cache	Shared L2 cache	planned	FPGA + ASIC	Very hard
of_cpu_llc_partitioned	Last-level cache slice with QoS	planned	FPGA + ASIC	Very hard
of_cpu_prefetcher	Hardware data prefetcher	planned	FPGA + ASIC	Medium
of_cpu_tcm_ctrl	Tightly coupled memory controller	simulated	FPGA + ASIC	Easy
of_cpu_xip_cache	Execute-in-place flash cache	planned	FPGA + ASIC	Medium

debug

7 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_debug_module	RISC-V debug module	simulated	FPGA + ASIC	Medium
of_cpu_jtag_dtm	JTAG debug transport module	fpga-routed	FPGA + ASIC	Easy
of_cpu_trigger_module	Debug trigger module	planned	FPGA + ASIC	Medium
of_cpu_cross_trigger	Multicore cross-trigger matrix	planned	FPGA + ASIC	Easy
of_cpu_hpm_counters	Performance monitor counters	planned	FPGA + ASIC	Easy
of_cpu_ras_reri	RAS error record unit	planned	FPGA + ASIC	Medium
of_cpu_pc_profiler	PC sampling profiler	planned	FPGA + ASIC	Easy

trace

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_trace_etrace	E-Trace instruction trace encoder	planned	FPGA + ASIC	Hard
of_cpu_trace_ntrace	N-Trace encoder	planned	FPGA + ASIC	Hard
of_cpu_trace_sink	Trace funnel and sink	planned	FPGA + ASIC	Medium

interrupt

5 blocks · 3 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_plic	Platform-level interrupt controller	simulated	FPGA + ASIC	Easy
of_cpu_aclint	Core-local interruptor (ACLINT)	simulated	FPGA + ASIC	Easy
of_cpu_clic	Core-local interrupt controller (CLIC)	simulated	FPGA + ASIC	Medium
of_cpu_aia	Advanced interrupt architecture (APLIC and IMSIC)	planned	FPGA + ASIC	Hard
of_cpu_mailbox	Inter-processor mailbox and semaphores	planned	FPGA + ASIC	Easy

mcu_subsystem

10 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_mcu_subsys_basic	Basic RV32 microcontroller subsystem	simulated	FPGA + ASIC	Medium
of_cpu_mcu_subsys_lowpower	Low-power IoT MCU subsystem	planned	FPGA + ASIC	Hard
of_cpu_mcu_subsys_auto	Automotive MCU subsystem	planned	FPGA + ASIC	Hard
of_cpu_soc_mgmt	SoC management controller	simulated	FPGA + ASIC	Medium
of_cpu_power_ctrl	Core power and clock controller	planned	FPGA + ASIC	Medium
of_cpu_hw_rtos	Hardware RTOS scheduler	planned	FPGA + ASIC	Medium
of_cpu_pio	Programmable I/O state machines	planned	FPGA + ASIC	Medium
of_cpu_microsequencer	Programmable microsequencer	planned	FPGA + ASIC	Easy
of_cpu_amo_unit	Far atomic memory operation unit	planned	FPGA + ASIC	Medium
of_cpu_boot_ctrl	Multi-source boot controller	planned	FPGA + ASIC	Medium

linux_soc

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_linux_soc	Embedded Linux SoC subsystem	planned	FPGA + ASIC	Very hard

legacy

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_mcs51_compat	MCS-51 compatible 8-bit core	planned	FPGA + ASIC	Medium

fpga_soft

4 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_fpga_soft_rv32	Configurable FPGA soft RV32 core	simulated	FPGA + ASIC	Medium
of_cpu_fpga_soft_tiny	Size-optimised FPGA soft core	planned	FPGA + ASIC	Easy
of_cpu_fpga_soft_mcu	FPGA soft microcontroller SoC	planned	FPGA + ASIC	Medium
of_cpu_fpga_soft_linux	FPGA Linux-capable soft SoC	planned	FPGA + ASIC	Hard

radhard

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_cpu_radhard_rv32	Radiation-tolerant RV32 core	planned	FPGA + ASIC	Hard
of_cpu_radhard_rv64	Radiation-tolerant RV64 core	planned	FPGA + ASIC	Very hard
of_cpu_radhard_obc	Spacecraft on-board computer subsystem	planned	FPGA + ASIC	Very hard
of_cpu_mem_scrubber	Memory EDAC scrubber	planned	FPGA + ASIC	Easy

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