of_cpu_pmp_unit
PMP and ePMP checker
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Physical memory protection unit with 0 to 64 regions, TOR/NA4/NAPOT matching and Smepmp machine-mode lockdown, reusable across cores.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| req | in | valid-qualified bus | 64 | |
| fault | out | valid-qualified bus | 8 |
Standards
- RISC-V Privileged 1.12
- RISC-V Smepmp 1.0
More in mmu
| ID | Block | Maturity |
|---|---|---|
| of_cpu_mmu | MMU with TLBs and page table walker | planned |