of_cpu_radhard_rv64
Radiation-tolerant RV64 core
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
RV64GC application core with parity and ECC on caches and TLBs, cache line scrubbing and error containment for on-board payload computing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 | |
| seu_evt | out | parallel | 4 |
Standards
- RISC-V RV64GC
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in radhard
| ID | Block | Maturity |
|---|---|---|
| of_cpu_radhard_rv32 | Radiation-tolerant RV32 core | planned |
| of_cpu_radhard_obc | Spacecraft on-board computer subsystem | planned |
| of_cpu_mem_scrubber | Memory EDAC scrubber | planned |