IP PortfolioProcessorsriscv_rt
of_cpu_rv32_rt_clic
Real-time RV32 core with CLIC
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Deterministic RV32IMC core with a core-local interrupt controller, hardware register stacking on interrupt entry, vectored and nested interrupts and fixed-latency TCM access.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 64 | |
| debug_req | in | serial | 1 |
Standards
- RISC-V RV32IMC
- RISC-V CLIC (draft)
- RISC-V Zcmp
- RISC-V Debug 0.13
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_rt
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv64_realtime | RV64 real-time core with MPU | planned |