IP PortfolioProcessorsriscv_mcu
of_cpu_rv32e_tiny
RV32E minimal core
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Two-stage in-order RV32E core with 16 integer registers, machine mode only and an optional iterative multiplier, sized for state machines and housekeeping controllers.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 8 |
Standards
- RISC-V RV32E
- RISC-V Zicsr
- RISC-V Privileged 1.12
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_mcu
| ID | Block | Maturity |
|---|---|---|
| of_cpu_rv32_bitserial | Bit-serial RV32I core | planned |
| of_cpu_rv32imc_mcu | RV32IMC microcontroller core | simulated |
| of_cpu_rv32imac_zc_mcu | RV32IMAC core with Zb and Zc | planned |
| of_cpu_rv32imfc_perf | RV32IMFC performance MCU core | simulated |
| of_cpu_rv32_dual_issue | Dual-issue in-order RV32 core | planned |