of_dsp_motor_control
Motor control coprocessor
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Coprocessor with Clarke/Park transforms, CORDIC, PI controllers and PWM-synchronous triggering for field-oriented motor control.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| adc_in | in | valid-qualified bus | 48 | |
| pwm_duty | out | valid-qualified bus | 48 |
Standards
No external standard applies.
More in dsp
| ID | Block | Maturity |
|---|---|---|
| of_dsp_vliw | VLIW DSP core | planned |
| of_dsp_audio | Audio DSP core | planned |
| of_dsp_baseband | Baseband DSP core | planned |
| of_dsp_vision | Vision DSP core | planned |
| of_dsp_radar | Radar signal processing DSP | planned |
| of_dsp_sensor_hub | Sensor fusion DSP | planned |