IP PortfolioQuantum controlsc_control
of_q_iq_modulator
Digital IQ modulator
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Digital upconversion of IQ envelopes with an NCO, interpolation filters and IQ gain, phase and offset correction for mixers or direct RF synthesis.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| iq_in | in | AXI4-Stream | 64 | |
| dac_out | out | AXI4-Stream | 256 |
Standards
No external standard applies.
More in sc_control
| ID | Block | Maturity |
|---|---|---|
| of_q_awg_sequencer | AWG pulse sequencer | planned |
| of_q_drag_gen | DRAG pulse generator | simulated |
| of_q_nco_bank | Phase-coherent NCO bank | simulated |
| of_q_readout_comb | Multiplexed readout tone generator | simulated |
| of_q_flux_ctrl | Flux bias DAC controller | simulated |
| of_q_flux_predistort | Flux pulse predistortion filter | simulated |
| of_q_fluxonium_drive | Low-frequency qubit drive synthesiser | planned |
| of_q_wave_decomp | Waveform memory decompressor | planned |
| of_q_dd_inserter | Dynamical decoupling inserter | planned |