IP PortfolioQuantum control

Quantum computing control and readout

Qubit control pulse generation, readout and demodulation, cryo-CMOS, QEC decoding, timing and synchronisation for superconducting, trapped-ion, photonic, spin and neutral-atom QPUs.

Blocks 87Implemented 21Families 13III-V process 1 · ASIC (CMOS) only 14 · FPGA + ASIC 72

sc_control 10 sc_readout 4 calibration 7 trapped_ion 7 atomic_optics 4 neutral_atom 3 spin_qubit 4 photonic 12 cryo_cmos 11 qec 12 timing 3 control_plane 6 quantum_sensing 4

sc_control

10 blocks · 6 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_awg_sequencer	AWG pulse sequencer	planned	FPGA + ASIC	Hard
of_q_drag_gen	DRAG pulse generator	simulated	FPGA + ASIC	Medium
of_q_iq_modulator	Digital IQ modulator	simulated	FPGA + ASIC	Medium
of_q_nco_bank	Phase-coherent NCO bank	simulated	FPGA + ASIC	Medium
of_q_readout_comb	Multiplexed readout tone generator	simulated	FPGA + ASIC	Medium
of_q_flux_ctrl	Flux bias DAC controller	simulated	FPGA + ASIC	Medium
of_q_flux_predistort	Flux pulse predistortion filter	simulated	FPGA + ASIC	Medium
of_q_fluxonium_drive	Low-frequency qubit drive synthesiser	planned	FPGA + ASIC	Medium
of_q_wave_decomp	Waveform memory decompressor	planned	FPGA + ASIC	Medium
of_q_dd_inserter	Dynamical decoupling inserter	planned	FPGA + ASIC	Medium

sc_readout

4 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_readout_demod	Frequency-multiplexed readout demodulator	planned	FPGA + ASIC	Hard
of_q_state_classifier	Qubit state classifier	simulated	FPGA + ASIC	Medium
of_q_paramp_pump	Parametric amplifier pump controller	planned	FPGA + ASIC	Medium
of_q_trace_capture	Raw readout trace capture	planned	FPGA + ASIC	Easy

calibration

7 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_mixer_cal	IQ mixer calibration engine	planned	FPGA + ASIC	Medium
of_q_cal_sweep	Calibration sweep and fit engine	simulated	FPGA + ASIC	Medium
of_q_readout_weights	Readout integration weight optimiser	planned	FPGA + ASIC	Medium
of_q_drift_tracker	Qubit parameter drift tracker	planned	FPGA + ASIC	Medium
of_q_crosstalk_comp	Crosstalk compensation matrix	planned	FPGA + ASIC	Medium
of_q_rb_engine	Randomised benchmarking sequence engine	planned	FPGA + ASIC	Medium
of_q_error_mitigation	Readout error mitigation engine	planned	FPGA + ASIC	Easy

trapped_ion

7 blocks · 3 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_aom_dds	AOM RF tone generator	simulated	FPGA + ASIC	Medium
of_q_aod_multitone	AOD multi-tone synthesiser	planned	FPGA + ASIC	Hard
of_q_photon_counter	Photon counting and state detection	simulated	FPGA + ASIC	Easy
of_q_ttl_sequencer	TTL and laser shutter sequencer	simulated	FPGA + ASIC	Medium
of_q_ion_transport	Ion transport waveform engine	planned	FPGA + ASIC	Hard
of_q_trap_rf_stab	Trap RF amplitude stabiliser	planned	FPGA + ASIC	Medium
of_q_ion_gate_pulse	Ion entangling gate pulse shaper	planned	FPGA + ASIC	Hard

atomic_optics

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_laser_lock	Laser frequency lock servo	planned	FPGA + ASIC	Medium
of_q_pid_bank	Multi-channel PID servo bank	planned	FPGA + ASIC	Easy
of_q_bfield_ctrl	Magnetic field coil controller	planned	FPGA + ASIC	Easy
of_q_comb_lock	Optical frequency comb stabiliser	planned	FPGA + ASIC	Medium

neutral_atom

3 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_tweezer_ctrl	Optical tweezer array controller	planned	FPGA + ASIC	Hard
of_q_camera_detect	Camera-based qubit state detection	simulated	FPGA + ASIC	Medium
of_q_slm_ctrl	Spatial light modulator controller	planned	FPGA + ASIC	Medium

spin_qubit

4 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_gate_dac_seq	Gate voltage DAC sequencer	simulated	FPGA + ASIC	Medium
of_q_rf_reflectometry	RF reflectometry readout	simulated	FPGA + ASIC	Medium
of_q_charge_sensor_lock	Charge sensor operating point feedback	planned	FPGA + ASIC	Easy
of_q_spin_shuttle	Spin conveyor shuttling generator	planned	FPGA + ASIC	Medium

photonic

12 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_snspd_readout	SNSPD readout front end	planned	ASIC (CMOS) only	Hard
of_q_spad_ctrl	SPAD gating and quench controller	planned	ASIC (CMOS) only	Hard
of_q_time_tagger	Multi-channel time tagger	planned	FPGA + ASIC	Hard
of_q_coincidence	Coincidence counter	simulated	FPGA + ASIC	Medium
of_q_tcspc_hist	TCSPC histogrammer	planned	FPGA + ASIC	Medium
of_q_feedforward	Feed-forward switch controller	planned	FPGA + ASIC	Hard
of_q_source_mux	Heralded source multiplexing controller	planned	FPGA + ASIC	Hard
of_q_pnr_analyser	Photon-number pulse analyser	planned	FPGA + ASIC	Medium
of_q_qkd_postproc	QKD post-processing engine	planned	FPGA + ASIC	Hard
of_q_qrng_frontend	Quantum RNG readout and extractor	planned	FPGA + ASIC	Medium
of_q_mbqc_ctrl	Measurement-based computation controller	planned	FPGA + ASIC	Hard
of_gaas_quantum_photon_src	AlGaAs entangled-photon and quantum-dot single-photon source	planned	III-V process	Very hard

cryo_cmos

11 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_cryo_ldo	Cryogenic LDO regulator	planned	ASIC (CMOS) only	Hard
of_q_cryo_dac	Cryogenic DAC	planned	ASIC (CMOS) only	Very hard
of_q_cryo_adc	Cryogenic ADC	planned	ASIC (CMOS) only	Very hard
of_q_cryo_readout_rx	Cryogenic readout receiver	planned	ASIC (CMOS) only	Very hard
of_q_cryo_serdes	Cryogenic serial link	planned	ASIC (CMOS) only	Very hard
of_q_cryo_controller	Low-power cryogenic controller	planned	ASIC (CMOS) only	Very hard
of_q_cryo_bias	Cryogenic bias generator	planned	ASIC (CMOS) only	Hard
of_q_cryo_mux	Cryogenic analog multiplexer	planned	ASIC (CMOS) only	Hard
of_q_cryo_temp_sensor	Cryogenic on-die temperature sensor	planned	ASIC (CMOS) only	Hard
of_q_sfq_interface	SFQ to CMOS interface	planned	ASIC (CMOS) only	Very hard
of_q_cryo_clock	Cryogenic clock generator	planned	ASIC (CMOS) only	Very hard

qec

12 blocks · 3 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_qec_uf	Union-find surface code decoder	planned	FPGA + ASIC	Hard
of_q_qec_mwpm	Minimum-weight perfect matching accelerator	planned	FPGA + ASIC	Very hard
of_q_qec_lut	Lookup-table decoder	planned	FPGA + ASIC	Easy
of_q_qec_nn	Neural network decoder engine	planned	FPGA + ASIC	Hard
of_q_qec_bp_osd	Belief propagation decoder for qLDPC codes	planned	FPGA + ASIC	Very hard
of_q_qec_window	Sliding-window decoding coordinator	planned	FPGA + ASIC	Hard
of_q_syndrome_sched	Syndrome extraction scheduler	simulated	FPGA + ASIC	Medium
of_q_syndrome_net	Syndrome aggregation network	simulated	FPGA + ASIC	Medium
of_q_lattice_surgery	Lattice surgery scheduler	planned	FPGA + ASIC	Very hard
of_q_pauli_frame	Pauli frame tracker	simulated	FPGA + ASIC	Medium
of_q_feedback_ctrl	Real-time feedback controller	planned	FPGA + ASIC	Hard
of_q_erasure_detect	Erasure detection unit	planned	FPGA + ASIC	Medium

timing

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_tdc	Picosecond time-to-digital converter	planned	ASIC (CMOS) only	Hard
of_q_trigger_dist	Deterministic trigger distribution	planned	FPGA + ASIC	Hard
of_q_clock_sync	Multi-board clock synchronisation	planned	FPGA + ASIC	Hard

control_plane

6 blocks · 3 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_control_processor	QPU control processor	planned	FPGA + ASIC	Very hard
of_q_pulse_queue	Timed pulse instruction queue	simulated	FPGA + ASIC	Medium
of_q_host_if	Control plane host interface	simulated	FPGA + ASIC	Medium
of_q_shot_accumulator	Shot accumulator and histogrammer	simulated	FPGA + ASIC	Easy
of_q_variational_loop	Near-time variational optimiser	planned	FPGA + ASIC	Medium
of_q_entanglement_link	Inter-QPU entanglement link controller	planned	FPGA + ASIC	Hard

quantum_sensing

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_q_odmr_ctrl	NV centre ODMR controller	planned	FPGA + ASIC	Medium
of_q_lockin	Digital lock-in amplifier	planned	FPGA + ASIC	Easy
of_q_clock_servo	Atomic clock servo	planned	FPGA + ASIC	Medium
of_q_opm_ctrl	Optically pumped magnetometer controller	planned	FPGA + ASIC	Medium

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