of_q_state_classifier

Qubit state classifier

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

Real-time discrimination of integrated IQ points into qubit states using linear or small neural classifiers, including leakage state detection.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	APB control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
iq_in	in	AXI4-Stream	64
state_out	out	valid-qualified bus	8

Standards

No external standard applies.

More in sc_readout

ID	Block	Maturity
of_q_readout_demod	Frequency-multiplexed readout demodulator	planned
of_q_paramp_pump	Parametric amplifier pump controller	planned
of_q_trace_capture	Raw readout trace capture	planned