IP PortfolioSecurityanti_tamper
of_sec_alert_handler
Security alert handler
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Collects differentially signalled alerts from security IP, classifies and escalates them through timed responses up to key wipe and reset.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| alerts | in | parallel | 64 | |
| esc_out | out | parallel | 4 |
Standards
No external standard applies.
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in anti_tamper
| ID | Block | Maturity |
|---|---|---|
| of_sec_vglitch_det | Voltage glitch detector | planned |
| of_sec_clk_monitor | Clock glitch and frequency monitor | planned |
| of_sec_laser_det | Laser fault injection detector | planned |
| of_sec_temp_tamper | Temperature tamper detector | planned |
| of_sec_timing_sensor | Timing violation sensors | planned |
| of_sec_active_shield | Active shield mesh | planned |
| of_sec_zeroize | Zeroisation controller | planned |
| of_sec_em_fi_det | Electromagnetic fault injection detector | planned |