IP PortfolioSecurity

Security IP (excluding post-quantum products)

Classical cryptography, hashing, TRNG and PUF, key management, secure boot, root of trust, memory protection, anti-tamper and side-channel countermeasures. Post-quantum algorithms are Dyber products and are deliberately not in OFIP.

Blocks 90Implemented 15Families 18ASIC (CMOS) only 17 · FPGA + ASIC 73

aes 7 aead 2 regional_cipher 4 legacy_cipher 1 inline_crypto 9 hash 9 public_key 5 rng 6 puf 4 key_mgmt 3 root_of_trust 8 lifecycle 4 memory_protection 7 attestation 2 anti_tamper 9 side_channel 6 secure_debug 1 firmware_integrity 3

aes

7 blocks · 3 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_aes_core	AES block cipher core	simulated	FPGA + ASIC	Easy
of_sec_aes_modes	AES modes engine	simulated	FPGA + ASIC	Medium
of_sec_aes_gcm	AES-GCM authenticated encryption engine	planned	FPGA + ASIC	Hard
of_sec_aes_xts	AES-XTS storage encryption engine	simulated	FPGA + ASIC	Medium
of_sec_aes_masked	Side-channel protected AES	planned	FPGA + ASIC	Hard
of_sec_aes_keywrap	AES key wrap engine	planned	FPGA + ASIC	Easy
of_sec_aes_gcm_siv	AES-GCM-SIV engine	planned	FPGA + ASIC	Medium

aead

2 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_chacha_poly	ChaCha20-Poly1305 engine	simulated	FPGA + ASIC	Medium
of_sec_ascon	Ascon lightweight cryptography engine	planned	FPGA + ASIC	Easy

regional_cipher

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_sm4	SM4 block cipher engine	planned	FPGA + ASIC	Medium
of_sec_aria	ARIA block cipher engine	planned	FPGA + ASIC	Medium
of_sec_camellia	Camellia block cipher engine	planned	FPGA + ASIC	Medium
of_sec_mobile_ciphers	3GPP confidentiality and integrity engine	planned	FPGA + ASIC	Medium

legacy_cipher

1 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_tdes_legacy	Legacy Triple-DES engine	planned	FPGA + ASIC	Easy

inline_crypto

9 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_wlan_ccmp_gcmp	WLAN CCMP and GCMP inline engine	planned	FPGA + ASIC	Medium
of_sec_macsec	MACsec engine	planned	FPGA + ASIC	Hard
of_sec_ipsec	IPsec ESP engine	planned	FPGA + ASIC	Very hard
of_sec_tls_record	TLS record offload	planned	FPGA + ASIC	Hard
of_sec_pcie_ide	PCIe IDE engine	planned	FPGA + ASIC	Very hard
of_sec_cxl_ide	CXL IDE engine	planned	FPGA + ASIC	Very hard
of_sec_storage_inline	Inline storage crypto engine	planned	FPGA + ASIC	Hard
of_sec_crypto_dma	Descriptor-based crypto offload engine	planned	FPGA + ASIC	Hard
of_sec_sed_band_mgr	Self-encrypting drive band manager	planned	FPGA + ASIC	Hard

hash

9 blocks · 4 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_sha256	SHA-224/256 engine	fpga-routed	FPGA + ASIC	Easy
of_sec_sha512	SHA-384/512 engine	simulated	FPGA + ASIC	Easy
of_sec_sha3	SHA-3 and SHAKE engine	simulated	FPGA + ASIC	Medium
of_sec_kmac	Masked KMAC engine	planned	FPGA + ASIC	Hard
of_sec_sm3	SM3 hash engine	planned	FPGA + ASIC	Easy
of_sec_blake2	BLAKE2 engine	planned	FPGA + ASIC	Easy
of_sec_blake3	BLAKE3 engine	planned	FPGA + ASIC	Medium
of_sec_hmac	HMAC engine	simulated	FPGA + ASIC	Easy
of_sec_kdf	Key derivation function engine	planned	FPGA + ASIC	Medium

public_key

5 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_rsa	RSA engine	planned	FPGA + ASIC	Hard
of_sec_ecc	ECDSA and ECDH engine	planned	FPGA + ASIC	Hard
of_sec_eddsa_x25519	EdDSA and X25519 engine	planned	FPGA + ASIC	Hard
of_sec_sm2	SM2 public key engine	planned	FPGA + ASIC	Hard
of_sec_bignum	Programmable bignum accelerator	planned	FPGA + ASIC	Very hard

rng

6 blocks · 2 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_trng_ro	Ring-oscillator entropy source	planned	ASIC (CMOS) only	Hard
of_sec_trng_noise	Thermal-noise entropy source	planned	ASIC (CMOS) only	Very hard
of_sec_entropy_health	Entropy health tests and conditioner	simulated	FPGA + ASIC	Medium
of_sec_ctr_drbg	CTR_DRBG	simulated	FPGA + ASIC	Medium
of_sec_hash_drbg	Hash_DRBG and HMAC_DRBG	planned	FPGA + ASIC	Medium
of_sec_entropy_dist	Entropy distribution network	planned	FPGA + ASIC	Easy

puf

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_puf_sram	SRAM PUF	planned	ASIC (CMOS) only	Hard
of_sec_puf_ro	Ring-oscillator PUF	planned	ASIC (CMOS) only	Hard
of_sec_puf_analog	Analog mismatch PUF	planned	ASIC (CMOS) only	Very hard
of_sec_fuzzy_extractor	Fuzzy extractor	planned	FPGA + ASIC	Medium

key_mgmt

3 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_key_manager	Key manager	planned	FPGA + ASIC	Hard
of_sec_key_vault	Key vault	simulated	FPGA + ASIC	Medium
of_sec_key_ladder	Content protection key ladder	planned	FPGA + ASIC	Medium

root_of_trust

8 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_boot_rom	Secure boot ROM controller	simulated	FPGA + ASIC	Medium
of_sec_rot	Discrete-class root of trust subsystem	planned	FPGA + ASIC	Very hard
of_sec_rot_soc	Integrated SoC root of trust	planned	FPGA + ASIC	Very hard
of_sec_enclave	Secure enclave subsystem	planned	FPGA + ASIC	Very hard
of_sec_hsm_auto	Automotive hardware security module	planned	FPGA + ASIC	Very hard
of_sec_tpm	TPM 2.0 core	planned	FPGA + ASIC	Very hard
of_sec_selftest	Cryptographic self-test sequencer	planned	FPGA + ASIC	Medium
of_sec_mailbox	Access-controlled security mailbox	planned	FPGA + ASIC	Easy

lifecycle

4 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_otp_ctrl	OTP controller	planned	ASIC (CMOS) only	Hard
of_sec_lc_ctrl	Lifecycle controller	planned	FPGA + ASIC	Hard
of_sec_rollback_counter	Anti-rollback counter	planned	FPGA + ASIC	Easy
of_sec_bbram_rtc	Battery-backed key store with tamper inputs	planned	ASIC (CMOS) only	Hard

memory_protection

7 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_mem_encrypt	Inline memory encryption engine	planned	FPGA + ASIC	Hard
of_sec_mem_integrity	Memory integrity engine	planned	FPGA + ASIC	Very hard
of_sec_sram_scramble	SRAM scrambling controller	planned	FPGA + ASIC	Medium
of_sec_lowlat_cipher	Low-latency block cipher	planned	FPGA + ASIC	Medium
of_sec_iopmp	I/O physical memory protection	planned	FPGA + ASIC	Medium
of_sec_bus_firewall	Peripheral access firewall	planned	FPGA + ASIC	Medium
of_sec_mem_tagging	Memory tagging unit	planned	FPGA + ASIC	Hard

attestation

2 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_dice	DICE identity engine	simulated	FPGA + ASIC	Medium
of_sec_spdm	SPDM responder engine	planned	FPGA + ASIC	Hard

anti_tamper

9 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_vglitch_det	Voltage glitch detector	planned	ASIC (CMOS) only	Hard
of_sec_clk_monitor	Clock glitch and frequency monitor	planned	ASIC (CMOS) only	Medium
of_sec_laser_det	Laser fault injection detector	planned	ASIC (CMOS) only	Very hard
of_sec_temp_tamper	Temperature tamper detector	planned	ASIC (CMOS) only	Medium
of_sec_timing_sensor	Timing violation sensors	planned	ASIC (CMOS) only	Hard
of_sec_active_shield	Active shield mesh	planned	ASIC (CMOS) only	Hard
of_sec_alert_handler	Security alert handler	simulated	FPGA + ASIC	Medium
of_sec_zeroize	Zeroisation controller	planned	FPGA + ASIC	Medium
of_sec_em_fi_det	Electromagnetic fault injection detector	planned	ASIC (CMOS) only	Very hard

side_channel

6 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_masking_gadgets	Masked logic gadget library	planned	FPGA + ASIC	Hard
of_sec_noise_gen	Power noise generator	planned	ASIC (CMOS) only	Hard
of_sec_rand_delay	Random delay and dummy operation inserter	planned	FPGA + ASIC	Easy
of_sec_dual_rail_lib	Dual-rail precharge logic cells	planned	ASIC (CMOS) only	Very hard
of_sec_fault_detect	Crypto fault detection wrappers	planned	FPGA + ASIC	Medium
of_sec_iso_ldo	Crypto supply isolation regulator	planned	ASIC (CMOS) only	Very hard

secure_debug

1 blocks · 1 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_auth_debug	Authenticated debug unlock	simulated	FPGA + ASIC	Medium

firmware_integrity

3 blocks · 0 implemented

ID	Block	Maturity	Targets	Difficulty
of_sec_fw_monitor	Runtime firmware integrity monitor	planned	FPGA + ASIC	Medium
of_sec_cfi_monitor	Control-flow integrity monitor	planned	FPGA + ASIC	Hard
of_sec_pfr	Platform firmware resilience controller	planned	FPGA + ASIC	Hard

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