of_sec_auth_debug

Authenticated debug unlock

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

Challenge-response unlock of JTAG and debug module using a signed token tied to the device identity and lifecycle state.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	APB control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
dbg_en	out	serial	1

Standards

IEEE 1149.1
RISC-V Debug 0.13