IP PortfolioSecuritypublic_key
of_sec_bignum
Programmable bignum accelerator
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
Wide-word processor with its own instruction and data memories, Montgomery multiply and secure wipe, programmed to run RSA and ECC in firmware.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
No external standard applies.
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in public_key
| ID | Block | Maturity |
|---|---|---|
| of_sec_rsa | RSA engine | planned |
| of_sec_ecc | ECDSA and ECDH engine | planned |
| of_sec_eddsa_x25519 | EdDSA and X25519 engine | planned |
| of_sec_sm2 | SM2 public key engine | planned |