IP PortfolioSecuritymemory_protection
of_sec_mem_encrypt
Inline memory encryption engine
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
AES-XTS inline encryption on the DRAM path with per-region or per-domain keys and address tweaks, transparent to software.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
- NIST FIPS 197
- IEEE 1619-2018
More in memory_protection
| ID | Block | Maturity |
|---|---|---|
| of_sec_mem_integrity | Memory integrity engine | planned |
| of_sec_sram_scramble | SRAM scrambling controller | planned |
| of_sec_lowlat_cipher | Low-latency block cipher | planned |
| of_sec_iopmp | I/O physical memory protection | planned |
| of_sec_bus_firewall | Peripheral access firewall | planned |
| of_sec_mem_tagging | Memory tagging unit | planned |