IP PortfolioSecurityroot_of_trust
of_sec_rot
Discrete-class root of trust subsystem
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
Security microcontroller subsystem with hardened core, crypto engines, entropy, key manager, OTP, lifecycle and alert handling.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- NIST FIPS 140-3
- NIST SP 800-193
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in root_of_trust
| ID | Block | Maturity |
|---|---|---|
| of_sec_boot_rom | Secure boot ROM controller | simulated |
| of_sec_rot_soc | Integrated SoC root of trust | planned |
| of_sec_enclave | Secure enclave subsystem | planned |
| of_sec_hsm_auto | Automotive hardware security module | planned |
| of_sec_tpm | TPM 2.0 core | planned |
| of_sec_selftest | Cryptographic self-test sequencer | planned |
| of_sec_mailbox | Access-controlled security mailbox | planned |