of_sec_sm3
SM3 hash engine
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
SM3 cryptographic hash core with padding and multi-block streaming.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| msg_in | in | AXI4-Stream | 32 |
Standards
- GB/T 32905-2016
- ISO/IEC 10118-3:2018
More in hash
| ID | Block | Maturity |
|---|---|---|
| of_sec_sha256 | SHA-224/256 engine | fpga-routed |
| of_sec_sha512 | SHA-384/512 engine | simulated |
| of_sec_sha3 | SHA-3 and SHAKE engine | simulated |
| of_sec_kmac | Masked KMAC engine | planned |
| of_sec_blake2 | BLAKE2 engine | planned |
| of_sec_blake3 | BLAKE3 engine | planned |
| of_sec_hmac | HMAC engine | simulated |
| of_sec_kdf | Key derivation function engine | planned |