IP PortfolioSecurityinline_crypto
of_sec_storage_inline
Inline storage crypto engine
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Key-slot based XTS-AES engine between the host controller and storage media for UFS, eMMC and NVMe, with per-request key selection.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| data_in | in | AXI4-Stream | 256 | |
| data_out | out | AXI4-Stream | 256 |
Standards
- JEDEC JESD220 (UFS)
- NVM Express Base Specification 2.0
- IEEE 1619-2018
More in inline_crypto
| ID | Block | Maturity |
|---|---|---|
| of_sec_wlan_ccmp_gcmp | WLAN CCMP and GCMP inline engine | planned |
| of_sec_macsec | MACsec engine | planned |
| of_sec_ipsec | IPsec ESP engine | planned |
| of_sec_tls_record | TLS record offload | planned |
| of_sec_pcie_ide | PCIe IDE engine | planned |
| of_sec_cxl_ide | CXL IDE engine | planned |
| of_sec_crypto_dma | Descriptor-based crypto offload engine | planned |
| of_sec_sed_band_mgr | Self-encrypting drive band manager | planned |