of_ew_pdw_gen

Pulse descriptor word generator

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2

Detects pulses and measures time of arrival, pulse width, amplitude, frequency and intra-pulse modulation to emit pulse descriptor words.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
channels	in	AXI4-Stream	256
pdw	out	AXI4-Stream	128

Standards

No external standard applies.

More in ew_sigint

ID	Block	Maturity
of_ew_wb_channelizer	Wideband EW channelizer	planned
of_ew_deinterleaver	Pulse deinterleaver	planned
of_ew_df	Direction finding processor	planned
of_ew_spectrum_monitor	Real-time spectrum monitor	planned